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fm3164/FM31256 64-kbit/256-kbit integrated processor companion with f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-86391 rev. *c revised may 5, 2014 256-kbit (32 k 8) serial (spi) f-ram features 64-kbit/256-kbit ferroelectric random access memory (f-ram) ? logically organized as 8 k 8 (fm3164) / 32 k 8 (FM31256) ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endurance table) ? nodelay? writes ? advanced high-reliability ferroelectric process high integration device replaces multiple parts ? serial nonvolatile memory ? real time clock (rtc) ? low voltage reset ? watchdog timer ? early power-fail warning/nmi ? two 16-bit event counter ? serial number with write-lock for security real-time clock/calendar ? backup current at 2 v: 1.15 ? a at +25 ? c ? seconds through centuries in bcd format ? tracks leap years through 2099 ? uses standard 32.768 khz crystal (6 pf) ? software calibration ? supports battery or capacitor backup processor companion ? active-low reset output for v dd and watchdog ? programmable low-v dd reset trip point ? manual reset filtered and debounced ? programmable watchdog timer ? dual battery-backed event co unter tracks system intrusions or other events ? comparator for power-fail interrupt ? 64-bit programmable serial number with lock fast 2-wire serial interface (i 2 c) ? up to 1-mhz frequency ? supports legacy timings for 100 khz and 400 khz ? rtc, supervisor controlled via i 2 c interface ? device select pins for up to 4 memory devices low power consumption ? 1.5 ma active current at 1 mhz ? 150 ? a standby current operating voltage: v dd = 2.7 v to 5.5 v industrial temperature: ?40 ? c to +85 ? c 14-pin small outline integrat ed circuit (soic) package restriction of hazardous substances (rohs) compliant functional overview the fm3164/FM31256 device inte grates f-ram memory with the most commonly needed functions for processor-based systems. major features include nonvolatile memory, real time clock, low-v dd reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used fo r a power-fail (nmi) interrupt or any other purpose. the fm3164/FM31256 is a 64-kbit/256-kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes similar to a ram. this memory is truly nonvolatile rather t han battery backed. it provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by other nonvolatile memories. the fm3164/FM31256 is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom. the real time clock (rtc) provides time and date information in bcd format. it can be permanently powered from an external backup voltage source, either a battery or a capacitor. the timekeeper uses a common external 32.768 khz crystal and provides a calibration mode that allows software adjustment of timekeeping accuracy. the processor companion includes commonly needed cpu support functions. supervisory functions include a reset output signal controlled by either a low v dd condition or a watchdog timeout. rst goes active when v dd drops below a programmable threshold and remains active for 100 ms after v dd rises above the trip point. a programmable watchdog timer runs from 100 ms to 3 seconds. the watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host before the ti meout. a flag-bit indicates the source of the reset. a comparator on pfi compares an external input pin to the onboard 1.2 v reference. this is useful for generating a power-fail interrupt (nmi) but can be used for any purpose. the family also includes a programmable 64-bit serial number that can be locked making it unalterable. additionally it offers a dual battery-backed event counter that tracks the number of rising or falling edges detected on a dedicated input pin.
fm3164/FM31256 document number: 001-86391 rev. *c page 2 of 33 logic block diagram
fm3164/FM31256 document number: 001-86391 rev. *c page 3 of 33 contents pinout ................................................................................ 4 pin definitions .................................................................. 4 overview............................................................................ 5 memory architecture ............... .................................... 5 processor companion ..................................................... 5 processor supervisor .................................................. 5 manual reset .............................................................. 6 reset flags ................................................................. 6 early power fail comparator ...................................... 6 event counter ............................................................. 7 serial number ............................................................. 7 real-time clock operation............................................... 7 backup power ............................................................. 8 trickle charger............................................................ 8 calibration ................................................................... 9 crystal oscillator ......................................................... 9 layout recommendations............................................. 10 register map ................................................................... 13 i2c interface .................................................................... 19 stop condition (p)................................................... 19 start condition (s)................................................. 19 data/address transfer .............................................. 19 acknowledge / no-acknowledge ............................... 19 slave address ........................................................... 20 addressing overview - memory ................................ 20 addressing overview - rtc & companion ............... 20 data transfer ............................................................ 20 memory operation.......................................................... 21 memory write operation ........................................... 21 memory read operation ........................................... 21 rtc/companion write operation ............................. 23 rtc/companion read operation ............................. 23 addressing fram array in the fm3164/FM31256 family........................................................................ 23 maximum ratings........................................................... 24 operating range............................................................. 24 dc electrical characteristics ........................................ 24 data retention and endurance ..................................... 26 capacitance .................................................................... 26 thermal resistance........................................................ 26 ac test loads and waveforms..................................... 26 ac test conditions ................................................... 26 supervisor timing .......................................................... 27 ac switching characteristics ....................................... 28 ordering information...................................................... 29 ordering code definitions ...... ................................... 29 package diagram............................................................ 30 acronyms ........................................................................ 31 document conventions ................................................. 31 units of measure ....................................................... 31 document history page ................................................. 32 sales, solutions, and legal information ...................... 33 worldwide sales and design supp ort............. .......... 33 products .................................................................... 33 psoc? solutions ...................................................... 33 cypress developer community................................. 33 technical support .................. ................................... 33
fm3164/FM31256 document number: 001-86391 rev. *c page 4 of 33 pinout figure 1. 14-pin soic pinout cnt1 cnt2 a0 a1 cal/pfo rst pfi x1 x2 sda scl v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ss dd v bak pin definitions pin name i/o type description a1-a0 input device select address 1-0 . these pins are used to select one of up to 4 devices of the same type on the same i 2 c bus. to select the device, the address value on the three pins must match the corresponding bits contained in the slave address. the address pins are pulled down internally. sda input/output serial data/address . this is a bi-directional pin for the i 2 c interface. it is open-drain and is intended to be wire-or'd with other devices on the i 2 c bus. the input buffer incorporates a schmitt trigger for noise immunity and the output dr iver includes slope control for falling edges. an external pull-up resistor is required. scl input serial clock . the serial clock pin for the i 2 c interface. data is clocked out of the device on the falling edge, and into the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. cnt1, cnt2 input event counter inputs . these battery-backed inputs increment counters when an edge is detected on the corresponding cnt pin. the polarity is prog rammable. these pins should not be left floating. tie to ground if these pins are not used. x1, x2 input/output 32.768 khz crystal conne ction. when using an external oscillator, apply the clock to x1 and a dc mid-level to x2. these pins should be left unconnected if rtc is not used. rst input/output reset . this active-low output is open drain with weak pull-up. it is also an input when used as a manual reset. this pin should be left floating if unused. pfi input early power-fail input . typically connected to an unregulated power supply to detect an early power failure. this pin must be tied to ground if unused. cal/pfo output calibration/early power-fail output . in calibration mode, this pin supplies a 512 hz square-wave output for clock calibration. in normal operat ion, this is the early power-fail output. v bak power supply backup supply voltage . connected to a 3 v battery or a large value capacitor. if v dd < 3.6 v and no backup supply is used, this pin should be tied to v dd . if v dd > 3.6 v and no backup supply is used, this pin should be left floating and the vbc bit should be set in the rtc register 0bh. v ss power supply ground for the device. must be connected to the gr ound of the system. v dd power supply power supply input to the device.
fm3164/FM31256 document number: 001-86391 rev. *c page 5 of 33 overview the fm3164/FM31256 device comb ines a serial nonvolatile ram with a real time clock (rtc) and a processor companion. the companion is a highly integrated peripheral including a processor supervisor, a comparator used for early power-fail warning, nonvolatile event counters, and a 64-bit serial number. the fm3164/FM31256 integrates these complementary but distinct functions under a common interface in a single package. the product is organized as two logical devices. the first is a memory and the second is the companion which includes all the remaining functions. from the system perspective they appear to be two separate devices with unique ids on the serial bus. the memory is organized as a standalone nonvolatile i 2 c memory using standard device id value. the real time clock and supervisor functions are accessed with a separate i 2 c device id. this allows clock/calendar data to be read while maintaining the most recently used memory address. the clock and supervisor functions are controlled by 25 special function registers. the rtc and event counter circuits are maintained by the power source on the v bak pin, allowing them to operate from battery or backup capacitor power when v dd drops below a set threshold. each functional block is described below. memory architecture the fm3164/FM31256 device is available in memory size 64-kbit/256-kbit. the device uses two-byte addressing for the memory portion of the chip. th is makes the device software compatible with its standalone memory counterparts, but makes them compatible within the entire family. the memory array is logically organized as 8,192 8 bits / 32,768 8 bits and is accessed using an industry-standard i 2 c interface. the memory is based on f-ram technology. therefore it can be treated as ram and is read or written at the speed of the i 2 c bus with no delays for write operations. it also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. the i 2 c protocol is described on page 19 . the memory array can be write-protected by software. two bits in the processor companion area (wp1, wp0 in register 0bh) control the protection setting. ba sed on the setting, the protected addresses cannot be written and the i 2 c interface will not acknowledge any data to protected addresses. the special function registers containing these bits are described in detail below. processor companion in addition to nonvolatile ram, the fm3164/FM31256 incorporates a real time clock and highly integrated processor companion. the companion includes a low-v dd reset, a programmable watchdog timer, a battery-backed event counters, a comparator for earl y power-fail detection or other purposes, and a 64-bit serial number. processor supervisor supervisors provide a host processor two basic functions: detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. the fm3164/FM31256 has a reset pin (rst ) to drive a processor reset input during power faults, power-up, and software lockups. it is an open drain output with a weak internal pull-up to v dd . this allows other reset sources to be wire-or'd to the rst pin. when v dd is above the programmed trip point, rst output is pulled weakly to v dd . if v dd drops below the reset trip point voltage level (v tp ), the rst pin will be driven low. it will remain low until v dd falls too low for circuit operation which is the v rst level. when v dd rises again above v tp , rst continues to drive low for at least 100 ms (t rpu ) to ensure a robust system reset at a reliable v dd level. after t rpu has been met, the rst pin will return to the weak high state. while rst is asserted, serial bus activity is locked out even if a transaction occurred as v dd dropped below v tp . a memory operation started while v dd is above v tp will be completed internally. ta b l e 1 below shows how bits vtp(1:0) control the trip point of the low-v dd reset. they are located in register 0bh, bits 1 and 0. the reset pin will drive low when v dd is below the selected v tp voltage, and the i 2 c interface and f-ram array will be locked out. figure 2 illustrates the reset operation in response to a low v dd . a watchdog timer can also be used to drive an active reset signal. the watchdog is a free-running programmable timer. the timeout period can be software programmed from 100 ms to 3 table 1. block memory write protection wp1 wp0 protected address range 0 0 none 0 1 bottom 1/4 1 0 bottom 1/2 11 full array table 2. vtp setting vtp setting vtp1 vtp0 2.6 v 0 0 2.9 v 0 1 3.9 v 1 0 4.4 v 1 1 figure 2. low v dd reset v dd v tp t rpu rst
fm3164/FM31256 document number: 001-86391 rev. *c page 6 of 33 seconds in 100 ms increments via a 5-bit nonvolatile register. all programmed settings are minimum values and vary with temperature according to the operating specifications. the watchdog has two additional controls associated with its operation, a watchdog enable bit (wde) and timer restart bits (wr). both the enable bit must be set and the watchdog must timeout in order to drive rst active. if a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. if wde = ?0?, the watchdog timer runs but a watchdog fault will not cause rst to be asserted low. the wtr flag will be set, indicating a watchdog fault. this setting is useful during software development if the developer does not want rst to drive. note that setting the maximum timeout setting (11111b) disables the counter to save power. the second control is a nibble that restarts the timer preventing a reset. the timer should be restarted after changing the timeout value. the watchdog timeout value is located in register 0ah, bits 4:0, and the watchdog enable is bit 7. the watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. writing this pattern will also cause the timer to load new timeout values. writing other patterns to this address will not affect its operation. note the watchdog ti mer is free-running. prior to enabling it, users should restart the timer as described above. this assures that the full timeout period will be set immediately after enabling. the watchdog is disabled when v dd is below v tp . the following table summarizes the watchdog bits. a block diagram follows. manual reset the rst is a bi-directional signal allowing the fm3164/FM31256 to filter and de-bounce a manual reset switch. the rst input detects an external low condition and responds by driving the rst signal low for 100 ms. note the internal weak pull-up eliminates the need for additional external components. reset flags in case of a reset condition, a flag bit will be set to indicate the source of the reset. a low-v dd reset is indicated by the por flag, register 09h, bit 6. a watchdog re set is indicated by the wtr flag, register 09h, bit 7. note that the flags are internally set in response to reset sources, but they must be cleared by the user. when the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. early power fail comparator an early power fail warning can be provided to the processor well before v dd drops out of spec. the comparator is used to create a power fail interrupt (nmi). this can be accomplished by connecting the pfi pin to the unregulated power supply via a resistor divider. an application circuit is shown below. the voltage on the pfi input pin is compared to an onboard 1.2 v reference. when the pfi input voltage drops below this threshold, the comparator will drive the cal/pfo pin to a low state. the comparator has 100 mv (max) of hysteresis to reduce noise sensitivity, only for a risi ng pfi signal. for a falling pfi edge, there is no hysteresis. watchdog timeout wdt(4:0) 0ah, bits 4:0 watchdog enable wde 0ah, bit 7 watchdog restart wr(3:0) 09h, bits 3:0 figure 3. watchdog timer timebase down counte r watchdog timer settings 100 m s clock wde rst wr ( 3:0 ) = 1010b to restart figure 4. manual reset figure 5. comparator as a power-fail warning fm3164/FM31256 rese t switch rst mcu rst fm31 64/FM31256 drives 100 ms ( min. ) behavior switch + - 1.2 v ref re g ulator v dd fm3164/ FM31256 cal/pfo pfi to mcu nmi in p ut
fm3164/FM31256 document number: 001-86391 rev. *c page 7 of 33 the comparator is a general purpose device and its application is not limited to the nmi function. the comparator is not integrated into the special function registers except as it shares it s output pin with the cal output. when the rtc calibration mode is invoked by setting the cal bit (register 00h, bit 2), the cal/pfo output pin will be driven with a 512 hz square wave and the comparator will be ignored. since most users only invoke the calibration mode during production, this should have no impact on system operations using the comparator. note the maximum voltage on the comparator input pfi is limited to 3.75 v under normal operating conditions. event counter the fm3164/FM31256 offers the user two battery-backed event counters. input pins cnt1 and cnt2 are programmable edge detectors. each clocks a 16-bit counter. when an edge occurs, the counters will increment their re spective registers. counter 1 is located in registers 0dh and 0eh, counter 2 is located in registers 0fh and 10h. these register values can be read anytime v dd is above v tp , and they will be incremented as long as a valid v bak power source is provided. to read, set the rc bit (register 0ch, bit 3) to 1. this takes a snapshot of all four counter bytes allowing a stable value even if a count occurs during the read. the registers can be written by software allowing the counters to be cl eared or initialized by the system. counts are blocked during a write operation. the two counters can be cascaded to create a single 32-bit counter by setting the cc control bit (register 0ch, bit 2). when cascaded, the cnt1 input will cause the counter to increment. cnt2 is not used in this mode and should be tied to ground. the control bits for event counti ng are located in register 0ch. counter 1 polarity is bit c1p, bit 0; counter 2 polarity is c2p, bit 1; the cascade control is cc, bit 2; and the read counter bit is rc, bit 3. the polarity bits must be set prior to setting the counter value(s). if a polarity bit is changed, the counter may inadvertently increment. if the counter pins are not being used, tie them to ground. serial number a memory location to write a 64-bit serial number is provided. it is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. the 8 bytes of data and the lock bit are all accessed via the device id for the processor companion. therefore the serial number area is separate and distinct from the memory array. the serial number registers can be written an unlimited number of times, so these locations are general purpose memory. however, once the lock bit is set, the values cannot be altered and the lock cannot be removed. once locked the serial number regist ers can still be read by the system. the serial number is located in registers 11h to 18h. the lock bit is snl (register 0bh, bit 7). setting the snl bit to a ?1? disables writes to the serial number registers, and the snl bit cannot be cleared. real-time clock operation the real-time clock (rtc) is a timekeeping device that can be battery or capacitor backed for permanently-powered operation. it offers a software calibration feature that allows high accuracy. the rtc consists of an oscillator, clock divider, and a register system for user access. it divides down the 32.768 khz time-base and provides a minimum resolution of seconds (1 hz). static registers provide the user with read/write access to the time values. it includes register s for seconds, minutes, hours, day-of-the-week, date, months, and years. a block diagram ( figure 7 ) illustrates the rtc function. the user registers are synchronized with the timekeeper core using r and w bits in register 00h described below. changing the r bit from ?0? to ?1? transfer s timekeeping information from the core into holding registers that can be read by the user. if a timekeeper update is pending when r is set, then the core will be updated prior to loading the us er registers. the registers are frozen and will not be updated again until the r bit is cleared to ?0?. r is used for reading the time. setting the w bit to ?1? locks the us er registers. clearing it to ?0? causes the values in the user registers to be loaded into the timekeeper core. w bit is used for writing new time values. users should be certain not to load invalid values, such as ffh, to the timekeeping registers. updates to the timekeeping core occur continuously except when locked. figure 6. event counter 16- bit c ount er cnt1 cc cnt2 c1p c2p 16- bit c ount er
fm3164/FM31256 document number: 001-86391 rev. *c page 8 of 33 backup power the real-time clock/calendar is intended to be permanently powered. when the primary system power fails, the voltage on the v dd pin will drop. when v dd is less than 2.5 v, the rtc (and event counters) will switch to the backup power supply on v bak . the clock operates at extremely low current in order to maximize battery or capacitor life. howeve r, an advantage of combining a clock function with f-ram memory is that data is not lost regardless of the backup power source. the i bak current varies with temperature and voltage (see dc electrical characteristics table). the following graph shows i bak as a function of v bak . these curves are useful for calculating backup time when a capacitor is used as the v bak source. the minimum v bak voltage varies linearly with temperature. the user can expect the minimum v bak voltage to be 1.23 v at +85 c and 1.90 v at -40 c. the te sted limit is 1.55 v at +25 c. note the minimum v bak voltage has been characterized at -40 c and +85 c but is not 100% tested. trickle charger to facilitate capacitor backup the v bak pin can optionally provide a trickle charge current. when the vbc bit (register 0bh, bit 2) is set to ?1?, the v bak pin will source approximately 15 a until v bak reaches v dd or 3.75 v, whichever is less. in 3 v systems, this charges the capacitor to v dd without an external diode and resistor charger. in 5 v systems, it provides the same convenience and also prevents the user from exceeding the v bak maximum voltage specification. figure 7. real-time clock core block diagram ? 32.768 khz crystal ? oscillator ? clock divider ? ? update logic ? ? 512 hz or square wave ? seconds 7 bits ? ? minutes 7 bits ? ? hours 6 bits ? ? date 6 bits ? ? months 5 bits ? ? years 8 bits ? ? ? days 3 bits ? ? user interface registers ? 1 hz ? ? w r oscen cf figure 8. i bak vs. v bak voltage i bak ( ? a) v bak (v) figure 9. v bak (min.) vs temperature temperature (c) v bakmin. (v)
fm3164/FM31256 document number: 001-86391 rev. *c page 9 of 33 in the case where no battery is used, the v bak pin should be tied according to the following conditions: for 3.3 v systems, v bak should be tied to v dd . this assumes v dd does not exceed 3.75 v. for 5 v systems, attach a 1 f capacitor to v bak and turn the trickle charger on. the v bak pin will charge to the internal backup voltage which regulates itself to about 3.6 v. v bak should not be tied to 5 v since the v bak (max) specification will be exceeded. a 1 f capacitor will keep the companion functions working for about 1.5 second. although v bak may be connected to v ss , this is not recommended if the companion is used. none of the companion functions will operate below about 2.5 v note systems using lithium batterie s should clear the vbc bit to ?0? to prevent battery charging. the v bak circuitry includes an internal 1 k ? series resistor as a safety element. calibration when the cal bit in the register 00h is set to ?1?, the clock enters calibration mode. in calibration mode, the cal/pfo output pin is dedicated to the calibration function and the power fail output is temporarily unavailable. calibr ation operates by applying a digital correction to the counter based on the frequency error. in this mode, the cal/pfo pin is dr iven with a 512 hz (nominal) square wave. any measured deviation from 512 hz translates into a timekeeping error. the user converts the measured error in ppm and writes the appropriate correction value to the calibration register. the correction factors are listed in the table below. positive ppm errors re quire a negative adjustment that removes pulses. negative ppm errors require a positive correction that adds pulses. positive ppm adjustments have the cals (sign) bit set to ?1?, whereas negative ppm adjustments have cals = ?0?. after calibration, the clock will have a maximum error of 2.17 ppm or 0.09 minu tes per month at the calibrated temperature. the calibration setting is stored in f-ram so it is not lost should the backup source fail. it is accessed with bits cal(4:0) in register 01h. this value can be written only when the cal bit is set to a ?1?. to exit the calibrat ion mode, the user must clear the cal bit to a ?0?. when the cal bit is ?0?, the cal/pfo pin will revert to the power fail output function. crystal oscillator the crystal oscillator is designed to use a 6 pf crystal without the need for external components, such as loading capacitors. the fm3164/FM31256 device has built-in loading capacitors that are optimized for use with 6 pf crystals. if a 32.768 khz crystal is not used, an external oscillator may be connected to the fm3164/FM31256. apply the oscillator to the x1 pin. its high and low voltage levels can be driven rail-to-rail or amplitudes as low as approximately 500 mv p-p. to ensure proper operation, a dc bias must be applied to the x2 pin. it should be centered between the high and low levels on the x1 pin. this can be accomplished with a voltage divider. in the example, r1 and r2 are chosen such that the x2 voltage is centered around the x1 oscill ator drive levels. if you wish to avoid the dc current, you may choose to drive x1 with an external clock and x2 with an inverted clock using a cmos inverter. figure 10. external oscillator fm3164/FM31256 v dd r1 r2 x1 x2
fm3164/FM31256 document number: 001-86391 rev. *c page 10 of 33 layout recommendations the x1 and x2 crystal pins employ very high impedance circuits and the oscillator connected to these pins can be upset by noise or extra loading. to reduce rtc clock errors from signal switching noise, a guard ring must be placed around these pads and the guard ring grounded. sda and scl traces should be routed away from the x1 / x2 pads. the x1 and x2 trace lengths should be less than 5 mm. the use of a ground plane on the backside or inner board layer is preferred. see layout example. red is the top layer, green is the bottom layer. figure 11. layout recommendations layout for surface mount crystal (red = top layer, green = bottom layer) layout for through hole crystal (red = top layer, green = bottom layer) vdd scl sd a x2 x1 pfi v ba k vdd scl sda x2 x1 pfi v bak
fm3164/FM31256 document number: 001-86391 rev. *c page 11 of 33 table 3. digital calibration adjustments positive calibration fo r slow clocks: calibration will ac hieve 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 511.9989 0 2.17 000000 1 511.9989 511.9967 2.18 6.51 100001 2 511.9967 511.9944 6.52 10.85 100010 3 511.9944 511.9922 10.86 15.19 100011 4 511.9922 511.9900 15.20 19.53 100100 5 511.9900 511.9878 19.54 23.87 100101 6 511.9878 511.9856 23.88 28.21 100110 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111
fm3164/FM31256 document number: 001-86391 rev. *c page 12 of 33 negative calibration for fast clocks: calibr ation will achieve 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111 table 3. digital calibration adjustments (continued)
fm3164/FM31256 document number: 001-86391 rev. *c page 13 of 33 register map the rtc and processor companion functions are accessed via 25 s pecial function registers, which are mapped to a separate i 2 c device id. the interface protocol is described on page 19 . the registers contain timekeeping data, control bits, and information flags. a description of each register follows the summary table. note when the device is first powered up and programmed, all time keeping registers must be written because the battery-backed register values cannot be guaranteed. the table below shows the default values of the non-volatile registers. all other registe r values should be treated as unknown. table 4. register map summary table address data function range d7 d6 d5 d4 d3 d2 d1 d0 18h serial number byte 7 serial number 7 ffh 17h serial number byte 6 serial number 6 ffh 16h serial number byte 5 serial number 5 ffh 15h serial number byte 4 serial number 4 ffh 14h serial number byte 3 serial number 3 ffh 13h serial number byte 2 serial number 2 ffh 12h serial number byte 1 serial number 1 ffh 11h serial number byte 0 serial number 0 ffh 10h counter 2 msb event counter 2 msb ffh 0fh counter 2 lsb event counter 2 lsb ffh 0eh counter 1 msb event counter 1 msb ffh 0dh counter 1 lsb event counter 1 lsb ffh 0ch rc cc c2p c1p event count control 0bh snl - - wp1 wp0 vbc vtp1 vtp0 companion control 0ah wde - - wdt4 wdt3 wdt2 wdt1 wdt0 watchdog control 09h wtr por lb - wr3 wr2 wr1 wr0 watchdog restart/flags 08h 10 years years years 00-99 07h 0 0 0 10 months months month 01-12 06h 0 0 10 date date date 01-31 05h00000 day day 01-07 04h 0 0 10 hours hours hours 00-23 03h 0 10 minutes minutes minutes 00-59 02h 0 10 seconds seconds seconds 00-59 01h oscen reserved cals cal4 cal3 cal2 cal1 cal0 cal control 00h reserved cf reserved reserved reserved cal w r rtc control table 5. default register values address hex value address hex value 18h 0x00 0ah 0x1f 17h 0x00 08h 0x00 16h 0x00 07h 0x01 15h 0x00 06h 0x01 14h 0x00 05h 0x01 13h 0x00 04h 0x00 12h 0x00 03h 0x01 11h 0x00 02h 0x00 0bh 0x00 01h 0x80 nonvolatile = battery-backed =
fm3164/FM31256 document number: 001-86391 rev. *c page 14 of 33 table 6. register description address description 18h serial number byte 7 d7 d6 d5 d4 d3 d2 d1 d0 sn.63 sn.62 sn.61 sn.60 sn.59 sn.58 sn.57 sn.56 upper byte of the serial number. read/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 17h serial number byte 6 d7 d6 d5 d4 d3 d2 d1 d0 sn.55 sn.54 sn.53 sn.52 sn.51 sn.50 sn.49 sn.48 16h byte 6 of the serial number. re ad/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. serial number byte 5 d7 d6 d5 d4 d3 d2 d1 d0 sn.47 sn.46 sn.45 sn.44 sn.43 sn.42 sn.41 sn.40 byte 5 of the serial number. re ad/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 15h serial number byte 4 d7 d6 d5 d4 d3 d2 d1 d0 sn.39 sn.38 sn.37 sn.36 sn.35 sn.34 sn.33 sn.32 byte 4 of the serial number. re ad/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 14h serial number byte 3 d7 d6 d5 d4 d3 d2 d1 d0 sn.31 sn.30 sn.29 sn.28 sn.27 sn.26 sn.25 sn.24 byte 3 of the serial number. re ad/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 13h serial number byte 2 d7 d6 d5 d4 d3 d2 d1 d0 sn.23 sn.22 sn.21 sn.20 sn.19 sn.18 sn.17 sn.16 byte 2 of the serial number. re ad/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 12h serial number byte 1 d7 d6 d5 d4 d3 d2 d1 d0 sn.15 sn.14 sn.13 sn.12 sn.11 sn.10 sn.9 sn.8 byte 1 of the serial number. re ad/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 11h serial number byte 0 d7 d6 d5 d4 d3 d2 d1 d0 sn.7 sn.6 sn.5 sn.4 sn.3 sn.2 sn.1 sn.0 lsb of the serial number. read/write when snl = ?0?, read-only when snl = ?1?. nonvolatile. 10h counter 2 msb d7 d6 d5 d4 d3 d2 d1 d0 c2.15 c2.14 c2.13 c2.12 c2.11 c2.10 c2.9 c2.8 event counter 2 msb. increments on overflows from counter 2 ls b. battery-backed, read/write.
fm3164/FM31256 document number: 001-86391 rev. *c page 15 of 33 0fh counter 2 lsb d7 d6 d5 d4 d3 d2 d1 d0 c2.7 c2.6 c2.5 c2.4 c2.3 c2.2 c2.1 c2.0 event counter 2 lsb. increments on programmed edge event on cnt2 input or overflows from counter 1 msb when cc = ?1?. battery-backed, read/write. 0eh counter 1 msb d7 d6 d5 d4 d3 d2 d1 d0 c1.15 c1.14 c1.13 c1.12 c1.11 c1.10 c1.9 c1.8 event counter 1msb. increments on overflows from counter 1 lsb. battery-backed, read/write. 0dh counter 1 lsb d7 d6 d5 d4 d3 d2 d1 d0 c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 event counter 1 lsb. increments on programmed edge event on cnt1 input. battery-backed, read/write. 0ch event counter control d7 d6 d5 d4 d3 d2 d1 d0 ----rc cc c2p c1p rc read counter. setting this bit to ?1? takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. th e rc bit will be automatically cleared. cc counter cascade. when cc = ?0?, the event counters operate independently accord ing to the edge programmed by c1p and c2p respectively. when cc = ?1?, the count ers are cascaded to create one 32-bit counter. the registers of counter 2 repres ent the most significant 16-bi ts of the counter and cnt1 is the controlling input. bit c2p is don't care when cc = ?1?. battery-backed, read/write. c2p cnt2 detects falling edges when c2p = ?0?, rising edges w hen c2p = ?1?. c2p is ?don't care? when cc = ?1?. the value of event counter 2 may inadvertently increm ent if c2p is changed. ba ttery-backed, read/write. c1p cnt1 detects falling edges when c1p = ?0?, rising ed ges when c1p = ?1?. the value of event counter 1 may inadvertently increment if c1p is ch anged. battery-backed, read/write. 0bh companion control d7 d6 d5 d4 d3 d2 d1 d0 snl - - wp1 wp0 vbc vtp1 vtp0 snl serial number lock: setting to a ?1? makes register s 11h to 18h and snl permanently read-only. snl cannot be cleared once set to ?1?. nonvolatile, read/write. wp(1:0) write protect. these bits c ontrol the write protecti on of the memory array. nonvolatile, read/write. write protect address wp1 wp0 none 0 0 bottom 1/4 0 1 bottom 1/2 1 0 full array 1 1 vbc v bak charger control. setting vbc to ?1? causes a 15 a trickle charge current to be supplied on v bak . clearing vbc to ?0? disables the charge current. nonvolatile, read/write. table 6. register description (continued) address description
fm3164/FM31256 document number: 001-86391 rev. *c page 16 of 33 vtp(1:0) vtp select. these bits control the reset trip point for the low v dd reset function. nonvolatile, read/write. vtp vtp1 vtp0 2.60 v 0 0 2.90 v 0 1 3.90 v 1 0 4.40 v 1 1 0ah watchdog control d7 d6 d5 d4 d3 d2 d1 d0 wde - - wdt4 wdt3 wdt2 wdt1 wdt0 wde watchdog enable. when wde = ?1?, a watchdog timer fault will cause the rst signal to go active. when wde = ?0? the timer runs but has no effect on rst , however the wtr flag will be set when a fault occurs. note as the timer is free-running, users should restart the timer using wr(3:0) prior to setting wde = ?1?. this assures a full watchdog timeout interval occurs . nonvolatile, read/write. wdt(4:0) watchdog timeout. indicates the minimum watchdog timeout interval with 100 ms resolution. new watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to wr(3:0). nonvolatile, read/write. watchdog timeout wdt4 wdt3 wdt2 wdt1 wdt0 invalid - default 100 ms 0 0 0 0 0 100 ms 00001 200 ms 00010 300 ms 00011 . . 2000 ms 1 0 1 0 0 2100 ms 1 0 1 0 1 2200 ms 1 0 1 1 0 . . 2900 ms 1 1 1 0 1 3000 ms 1 1 1 1 0 disable counter 1 1 1 1 1 09h watchdog restart and flags d7 d6 d5 d4 d3 d2 d1 d0 wtr por lb - wr3 wr2 wr1 wr0 wtr watchdog timer reset flag: when a watchdog timer fault o ccurs, the wtr bit will be set to ?1?. it must be cleared by the user. note that both wtr and por could be set if both reset sources have occurred since the flags were cleared by the user. battery-backed. read/write (internally set, user can clear bit). por power-on reset flag: when the rst pin is activated by v dd < v tp , the por bit will be set to ?1?. it must be cleared by the user. note that both wtr and por could be set if both reset sources have occurred since the flags were cleared by the user. battery-backed. read/write (internally set, user can clear bit). table 6. register description (continued) address description
fm3164/FM31256 document number: 001-86391 rev. *c page 17 of 33 lb low backup flag: on power up, if the v bak source is below the minimum voltage to operate the rtc and event counters, this bit will be set to ?1?. the user should cl ear it to ?0? when initializing the system. battery-backed. read/write (internally set, user can clear bit). wr(3:0) watchdog restart: writing a pattern 1010b to wr(3:0) restarts the watchdog timer. the upper nibble contents do not affect this operatio n. writing any pattern other than 1010b to wr(3:0 ) has no effect on the timer. this allows users to clear the wtr, por, and lb flags without a ffecting the watchdog timer. battery-backed, write-only. 08h timekeeping ? years d7 d6 d5 d4 d3 d2 d1 d0 10 year.3 10 year.2 10 year.1 10 year.0 year.3 year.2 year.1 year.0 contains the lower two bcd digits of the year. lower nibbl e contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0-99. battery-backed, read/write. 07h timekeeping ? months d7 d6 d5 d4 d3 d2 d1 d0 000 10 month month.3 month.2 month.1 month.0 contains the bcd digits for t he month. lower nibble contains the lower digi t and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the regist er is 1-12. battery-backed, read/write. 06h timekeeping ? date of the month d7 d6 d5 d4 d3 d2 d1 d0 00 10 date.1 10 date.0 date.3 date.2 date.1 date.0 contains the bcd digits for the date of the month. lower ni bble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1-31. battery-backed, read/write. 05h timekeeping ? day of the week d7 d6 d5 d4 d3 d2 d1 d0 00000 day.2 day.1 day.0 lower nibble contains a value that correlates to day of the we ek. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. battery-backed, read/write. 04h timekeeping ? hours d7 d6 d5 d4 d3 d2 d1 d0 00 10 hours.1 10 hours.0 hours.3 hours.2 hours.1 hours.0 contains the bcd value of hours in 24-hour format. lower ni bble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and ope rates from 0 to 2. the range for the register is 0-23. battery-backed, read/write. 03h timekeeping ? minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10 min.2 10 min.1 10 min.0 min.3 min.2 min.1 min.0 contains the bcd value of minutes. lower nibble contai ns the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0-59. battery-backed, read/write. table 6. register description (continued) address description
fm3164/FM31256 document number: 001-86391 rev. *c page 18 of 33 02h timekeeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10 sec.2 10 sec.1 10 sec.0 seconds.3 seconds.2 seconds.1 seconds.0 contains the bcd value of seconds. lower nibble contains t he lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the ra nge for the register is 0-59. battery-backed, read/write. 01h cal/control d7 d6 d5 d4 d3 d2 d1 d0 oscen reserved cals cal.4 cal.3 cal.2 cal.1 cal.0 oscen oscillator enable. when set to ?1?, t he oscillator is halted. when set to ?0?, the oscillator runs. disabling the oscillator can save battery power dur ing storage. on a power-up without ba ttery, this bit is set to ?1?. battery-backed, read/write. reserved reserved bits. do not use. should remain set to ?0?. cals calibration sign: determines if the ca libration adjustment is applied as an addi tion to or as a subtraction from the time-base. this bit can be written only when cal = ?1?. n onvolatile, read/write. cal(4:0) calibration setting: these five bits control the calibra tion of the clock. these bits can be written only when cal = ?1?. nonvolatile, read/write. 00h rtc control d7 d6 d5 d4 d3 d2 d1 d0 reserved cf reserved reserved reserved cal w r cf century overflow flag. this bit is set to a ?1? when the va lues in the years register ov erflows from 99 to 00. this indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. the user should record the new century information as needed. this bit is cleared to ?0? when the flag register is read. it is read-only for the user. battery-backed. cal calibration setting. when set to ?1?, the clock enters calibration mode. when cal is set to ?0?, the clock operates normally, and the cal/pfo pin is controlled by the power fail comparator. battery-backed, read/write. w write time. setting the w bit to ?1? freezes the clock. the user can then write the timekeeping registers with updated values. resetting the w bit to ?0? causes the c ontents of the time register s to be transferred to the timekeeping counters and restarts th e clock. battery-backed, read/write. r read time. setting the r bit to ?1? copies a static image of the timekeeping core and place it into the user registers. the user can then read them without concerns over changing values causing system errors. the r bit going from ?0? to ?1? causes the timekeeping captur e, so the bit must be returned to ?0 ? prior to reading again. battery-backed, read/write. reserved reserved bits. do not use. should remain set to ?0?. table 6. register description (continued) address description
fm3164/FM31256 document number: 001-86391 rev. *c page 19 of 33 i 2 c interface the fm3164/FM31256 employs an industry standard i 2 c bus that is familiar to many users. this product is unique since it incorporates two logical devices in one chip. each logical device can be accessed individually. although monolithic, it appears to the system software to be two separate products. one is a memory device. it has a slave address (slave id = 1010b) that operates the same as a stand-alone memory device. the second device is a real-time clock and processor companion which have a unique slave address (slave id = 1101b). by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling t he bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm3164/FM31256 is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 12 and figure 13 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electr ical specifications section. stop condition (p) a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm3164/FM31256 should end with a stop condition. if an operation is in progress when a stop is asserted, the operation will be aborted. the mast er must have control of sda in order to assert a stop condition. start condition (s) a start condition is indicated when the bus master drives sda from high to low while the sc l signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm3164/FM31256 for a new operation. if during operation the power supply drops below the specified v tp minimum, any i 2 c transaction in progress will be aborted and the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the three conditions described above, the sda signal should not change while scl is high. acknowledge / no-acknowledge the acknowledge takes place after the 8th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no-acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fa ils. in this case, the no-acknowledge ceases the current operation so that the device can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read figure 12. start and stop conditions figure 13. data transfer on the i 2 c bus full pagewidth sda scl p stop condition sda scl s start condition handbook, full pagewidth s or p sda s p scl stop or start condition s start condition 2 3 4 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from slave byte complete acknowledgement signal from receiver 1
fm3164/FM31256 document number: 001-86391 rev. *c page 20 of 33 operation, the fm3164/FM31256 will continue to place data onto the bus as long as the receiv er sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the receiver must not a cknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm3164/FM31256 to attempt to dr ive the bus on the next clock while the master is sending a new command such as stop. slave address the first byte that the fm3164/ FM31256 expects after a start condition is the slave address. as shown in figure 15 and figure 16 , the slave address contains the device type or slave id, the device select address bits, and a bit that specifies if the trans- action is a read or a write. the fm3164/FM31256 has two slave addresses (slave ids) associated with two logical devices. bits 7-4 are the device type (slave id) and should be set to 1010b for the memory device. the other logical device within the fm3164/FM31256 is the real-time clock and companion. bits 7-4 are the device type (slave id) and should be set to 1101b for the rtc and companion. a bus transaction with this slave address will not affect the memory in any way. the figures below illustrate the two slave addresses. bits 2-1 are the device select address bits. they must match the corresponding value on the external address pins to select the device. up to four fm3164/FM31256 devices can reside on the same i 2 c bus by assigning a different address to each. bit 0 is the read/write bit (r/w ). r/w = ?1? indicates a read operation and r/w = ?0? indicates a write operation. addressing overview - memory after the fm3164/FM31256 (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes. the complete 15-bit address is latched internally. each access causes the latched address value to be incremented automati- cally. the current address is the value that is held in the latch; either a newly written value or the address following the last access. the current address will be held for as long as v dd >v tp or until a new value is written. reads always use the current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm3164/FM31256 increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (7fffh) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. addressing overview - rtc & companion the rtc and processor companion operate in a similar manner to the memory, except that it uses only one byte of address. addresses 00h to 18h correspond to special function registers. attempting to load addresses above 18h is an illegal condition; the fm3164/FM31256 will return a nack and abort the i 2 c transaction. data transfer after the address bytes have been transmitted, data transfer between the bus master and the fm3164/FM31256 can begin. for a read operation the fm3164/FM31256 will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occurs, the fm3164/FM31256 will transfer the next sequential byte. if the acknowledge is not sent, the fm3164/FM31256 will end the read operation. for a write figure 14. acknowledge on the i 2 c bus handbook, full pagewidth s start condition 9 8 2 1 clock pulse for acknowledgement no acknowledge acknowledge data output by master data output by slave scl from master figure 15 memory slave device address figure 16 companion slave device address handbook, halfpage r/w lsb msb slave id 10 10 x a0 a1 device select handbook, halfpage r/w lsb msb slave id 11 01 x a0 a1 device select
fm3164/FM31256 document number: 001-86391 rev. *c page 21 of 33 operation, the fm3164/FM31256 will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm3164/FM31256 is designed to operate in a manner very similar to other i 2 c interface memory products. the major differ- ences result from the higher performance write capability of f-ram technology. these improvements result in some differ- ences between the fm3164/FM31256 and a similar configu- ration eeprom during writes. th e complete oper ation for both writes and reads is explained below. the memory address for fm3164 range from 0x0000 to 0x1ffff, and for FM31256, they range from 0x0000 to 0x7fff. memory functionality is described with respect to FM31256 in the following sections. memory write operation all writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the lsb of the slave address (r/w bit) to a '0'. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condit ion. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from 7fffh to 0000h. unlike other nonvolatile memory technologies, there is no effective write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through th e bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or writ e can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8th data bit. the fm3164/FM31256 uses no page buffering. figure 17 and figure 18 below illustrate a single-byte and multiple-byte write cycles. memory read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the fm3164/FM31256 uses the internal address latch to supply the address. in a select ive read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the fm3164/FM31256 uses an internal latch to supply the address for a read operation. a current address read uses the existing value in the address latch as a starting place for the read oper ation. the system reads from the address immediately following t hat of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a '1'. this indicates that a read operation is requested. after receiving the complete slave address, the fm3164/FM31256 will begin shifting out data from the current address on the next clock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current figure 17. single-byte write s a slave address 0 address msb a data byte a p by master by f-ram start address & data stop acknowledge address lsb a figure 18. multi-byte write s a slave address 0 address msb a data byte a p by master by f-ram start address & data stop acknowledge address lsb a data byte a
fm3164/FM31256 document number: 001-86391 rev. *c page 22 of 33 address read with multiple byte transfers. after each byte the internal address counter will be incremented. note each time the bus master acknowledges a byte, this indicates that the fm3164/fm 31256 should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the fm3164/FM31256 attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clo ck cycle. this is illustrated in the diagrams below. this is preferred. 2. the bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. 3. the bus master issues a stop in the 9th clock cycle. 4. the bus master issues a start in the 9th clock cycle. if the internal address reache s 7fffh, it will wrap around to 0000h on the next read cycle. figure 19 and figure 20 below show the proper operation for current address reads. selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb (r/w ) set to ?0?. this specifies a write operation. according to the writ e protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm3164/FM31256 acknowledges the address, the bus master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a '1'. the operation is now a current address read. figure 19. current address read figure 20. sequential read s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data data byte a acknowledge figure 21. selective (random) read s a slave address 1 data byte 1 p by master by f-ram start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a
fm3164/FM31256 document number: 001-86391 rev. *c page 23 of 33 rtc/companion write operation all rtc and companion writes operate in a similar manner to memory writes. the distinction is that a different device id is used and only one byte address is needed instead of two byte address. figure 22 illustrates a single byte write to this device. note although not required, it is recommended that a5-a7 in the register address byte are zeros in order to preserve compatibility with future devices. rtc/companion read operation as with writes, a read operation begins with the slave address. to perform a register read, t he bus master supplies a slave address with the lsb set to ?1?. this indicates that a read operation is requested. after receiving the complete slave address, the fm3164/FM31256 will begin shifting data out from the current register address on the next clock. auto-increment operates for the special functi on registers as with the memory address. a current address read for the registers look exactly like the memory except that the device id is different. the fm3164/FM31256 contains two separate address registers, one for the memory address and the other for the register address. this allows the contents of one address register to be modified without affecting the current address of the other register. for example, this would allow an interrupted read to the memory while still providing fast access to an rtc register. a subsequent memory read will then continue from the memory address where it previously left off, without requiring the load of a new memory address. however, a write sequence always requires an address to be supplied. addressing fram array in the fm3164/FM31256 family the fm3164/FM31256 family includes 64-kbit and 256-kbit memory densities. the following 2-byte address field is shown for each density. figure 22. single byte write s a slave address 0 a ddress a data byte a p by ma ste r star t a ddress & data stop a cknowledge 000 by f-ram part number 1 st address byte 2 nd address byte fm3164 x x x a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 FM31256 x a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
fm3164/FM31256 document number: 001-86391 rev. *c page 24 of 33 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ? c maximum junction temperature ................................... 95 ? c supply voltage on v dd relative to v ss .........?1.0 v to +7.0 v input voltage ........... ?1.0 v to +7.0 v and v in < v dd + 1.0 v backup supply voltage..................................?1.0 v to +4.5 v dc voltage applied to outputs in high-z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) .................................. 15 ma electrostatic discharge voltage human body model (jedec std jesd22-a114-e) .............. 2 kv charged device model (jedec std jesd22-c101-c) ..... 1.25 kv machine model (jedec std jesd22-a115-a) ..................... 100 v latch-up current .................................................. > 100 ma note pfi input voltage must not exceed 4.5 v. the "v in < v dd +1.0 v" restriction does not apply to the scl and sda inputs which do not employ a diode to v dd . operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 2.7 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [1] max unit v dd [2] power supply 2.7 ? 5.5 v i dd average v dd current scl toggling between v dd ? 0.3 v and v ss , other inputs v ss or v dd ? 0.3 v. f scl = 100 khz ? ? 500 ? a f scl = 400 khz ? ? 900 ? a f scl = 1 mhz ? ? 1500 ? a i sb v dd standby current scl = sda = v dd . all other inputs v ss or v dd . stop command issued. v dd < 5.5 v ? ? 150 ? a v dd < 3.6 v ? ? 120 ? a v bak [3] rtc backup voltage t a = +25 ? c to +85 ? c1.55?3.75v t a = ?40 ? c to +25 ? c1.90?3.75v i bak rtc backup current v dd < 2.4 v, oscillator running, cnt1, cnt 2 at v bak . t a = +25 ? c, v bak = 3.0 v ? ? 1.4 ? a t a = +85 ? c, v bak = 3.0 v ? ? 2.1 ? a t a = +25 ? c, v bak = 2.0 v ? ? 1.15 ? a t a = +85 ? c, v bak = 2.0 v ? ? 1.75 ? a i baktc [4] trickle charge current 5 ? 25 ? a notes 1. typical values are at 25 c, v dd = v dd (typ). not 100% tested. 2. full complete operation. supervisory circuits, rtc, etc operate to lower voltages as specified. 3. the v bak trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 4. v bak will source current when trickle charge is enabled (vbc bit = ?1?), v dd > v bak , and v bak < v bak max.
fm3164/FM31256 document number: 001-86391 rev. *c page 25 of 33 v tp0 v dd trip point voltage, vtp(1:0) = 00b rst is asserted active when v dd < v tp . 2.50 2.6 2.70 v v tp1 v dd trip point voltage, vtp(1:0) = 01b rst is asserted active when v dd < v tp . 2.802.903.00v v tp2 v dd trip point voltage, vtp(1:0) = 10b rst is asserted active when v dd < v tp . 3.753.904.00v v tp3 v dd trip point voltage, vtp(1:0) = 11b rst is asserted active when v dd < v tp . 4.204.404.50v v rst [5] v dd for valid rst i ol = 80 ? a at v ol v bak > v bak min 0 ? ? v v bak < v bak min 1.6 ? ? v i li input leakage current v ss < v in < v dd. does not apply to a0, a1, pfi, rst , x1, or x2 ??1 ? a i lo output leakage current v ss < v out < v dd . does not apply to rst , x1, or x2 ? ? 1 ? a v il [6] input low voltage all inputs except as listed below ? 0.3 ? 0.3 v dd v cnt1, cnt2 battery-backed (v dd < 2.5 v) ? 0.3 ? 0.5 v cnt1, cnt2 (v dd > 2.5 v) ? 0.3 ? 0.8 v v ih input high voltage all inputs except as listed below 0.7 v dd ?v dd + 0.3 v cnt1, cnt2 battery-backed (v dd < 2.5 v) v bak ? 0.5 ? v bak + 0.3 v cnt1, cnt2 (v dd > 2.5 v) 0.7 v dd ?v dd + 0.3 v pfi (comparator input) ? ? 3.75 v v oh output high voltage i oh = ?2 ma 2.4 ? ? v v ol output low voltage i ol = 3 ma ? ? 0.4 v r rst pull-up resistance for rst inactive 50 ? 400 k ? r in input resistance (a1-a0) for v in = v il (max ) 20 ? ? k ? for v in = v ih (min) 1 ? ? m ? v pfi power fail input reference voltage 1.140 1.20 1.225 v v hys power fail input (pfi) hysteresis (rising) ? ? 100 mv dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [1] max unit notes 5. the minimum v dd to guarantee the level of rst remains a valid v ol level. 6. includes rst input detection of external reset condition to trigger driving of rst signal by fm3164/FM31256.
fm3164/FM31256 document number: 001-86391 rev. *c page 26 of 33 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times .................................................10 ns input and output timing reference levels ................0.5 v dd output load capacitance ............................................ 100 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c 10 ? years t a = 75 ? c38? t a = 65 ? c151? nv c endurance over operating temperature 10 14 ? cycles capacitance parameter [7] description test conditions typ max unit c io input/output pin capacitance t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) ? 8 pf c xtl [8] x1, x2 crystal pin capacitance 12 ? pf thermal resistance parameter description test conditions 14-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 80 ? c/w ? jc thermal resistance (junction to case) 29 ? c/w ac test loads and waveforms figure 23. ac test loads and waveforms 5.5 v output 100 pf 1.7 k ? 7. this parameter is characterized and not 100% tested. 8. the crystal attached to the x1/x2 pins must be rated as 6 pf.
fm3164/FM31256 document number: 001-86391 rev. *c page 27 of 33 supervisor timing over the operating range parameter description min max units t rpu rst active (low) after v dd > v tp 100 200 ms t rnr [9] rst response time to v dd < v tp (noise filter) 10 25 ? s t vr [9, 10] v dd power-up ramp rate 50 - ? s/v t vf [9, 10] v dd power-down ramp rate 100 - ? s/v t wdp [11] pulse width of rst for watchdog reset 100 200 ms t wdog [11] timeout of watchdog t dog 2 t dog ms f cnt frequency of event counters 0 10 mhz figure 24. rst timing v dd t vf t vr t rnr 9. this parameter is characterized and not 100% tested. 10. slope measured at any point on v dd waveform. 11. t dog is the programmed time in register in register 0ah, v dd > v tp , and t rpu satisfied.
fm3164/FM31256 document number: 001-86391 rev. *c page 28 of 33 ac switching characteristics over the operating range parameter [12] alt. parameter description min max min max min max unit f scl scl clock frequency 0 100 0 400 0 1000 khz t su; sta start condition setup for repeated start 4.7 ? 0.6 ? 0.25 ? ? s t hd;sta start condition hold time 4.0 ? 0.6 ? 0.25 ? ? s t low clock low period 4.7 ? 1.3 ? 0.6 ? ? s t high clock high period 4.0 ? 0.6 ? 0.4 ? ? s t su;dat t su;data data in setup 250 ? 100 ? 100 ? ns t hd;dat t hd;data data in hold 0 ? 0 ? 0 ? ns t dh data output hold (from scl @ v il )0?0?0?ns t r [13] t r input rise time ? 1000 ? 300 ? 300 ns t f [13] t f input fall time ? 300 ? 300 ? 100 ns t su;sto stop condition setup 4 ? 0.6 0.25 ? ? s t aa t vd;data scl low to sda data out valid ? 3 0.9 ? 0.55 ? s t buf bus free before new transmission 4.7 ? 1.3 ? 0.5 ? ? s t sp noise suppression time constant on scl, sda ? 50 50 ? 50 ns figure 25. read bus timing diagram figure 26. write bus timing diagram t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:dat t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda notes 12. test conditions assume a signal transition time of 10 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , and output loading of the specified i ol /i oh and 100 pf load capacitance shown in page 26 . 13. this parameter is characterized and not 100% tested.
fm3164/FM31256 document number: 001-86391 rev. *c page 29 of 33 ordering code definitions ordering information ordering code package diagram package type operating range fm3164/FM31256-g 51-85067 14-pin soic industrial fm3164/FM31256-gtr 51-85067 14-pin soic all these parts are pb-free. contact your local cypre ss sales representative for availability of these parts. option: blank = standard; tr = tape and reel package type: g = 14-pin soic; density: 64 = 64-kbit; 256 = 256-kbit i 2 c processor companion cypress 31 fm 64 g tr -
fm3164/FM31256 document number: 001-86391 rev. *c page 30 of 33 package diagram figure 27. 14-pin soic (150 mils) package outline, 51-85067 51-85067 *d
fm3164/FM31256 document number: 001-86391 rev. *c page 31 of 33 acronyms document conventions units of measure acronym description eeprom electrically erasable programmable read-only memory eia electronic industries alliance f-ram ferroelectric random access memory i 2 c inter-integrated circuit i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit nmi non maskable interrupt rohs restriction of hazardous substances soic small outline integrated circuit symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mbit megabit mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
fm3164/FM31256 document number: 001-86391 rev. *c page 32 of 33 document history page document title: fm3164/FM31256, 64-kbit/256-kbit integrated processor companion with f-ram document number: 001-86391 rev. ecn no. orig. of change submission date description of change ** 3916896 gvch 02/28/2013 new spec *a 3924836 gvch 03/07/2013 modified formatting deleted 4kb and 8kb versions changed to production status *b 3985209 gvch 05/02/2013 changed following values v tp0 min value from 2.55 v to 2.50 v v tp1 min value from 2.85v to 2.80 v v tp2 min value from 3.80 v to 3.75 v v tp3 min value from 4.25 v to 4.20 v v pfi minvalue from 1.175 v to 1.140 v *c 4333096 gvch 05/059/2014 converted to cypress standard format updated maximum ratings table - removed moisture sensitivity level (msl) - added junction temperature and latch up current updated data retention and endurance table added thermal resistance table removed package marking scheme (top mark)
document number: 001-86391 rev. *c revised may 5, 2014 page 33 of 33 all products and company names mentioned in this document may be the trademarks of their respective holders. fm3164/FM31256 ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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